1. Field of the Invention
The present invention relates to a semiconductor package and a fabrication method thereof.
2. Background of the Related Art
A multi-layer substrate can be used for semiconductor packages, such as a PPGA PKG (Plastic Pin Grid Assay Package), a PBGA PKG (Plastic Ball Grid Array Package), a PLGA PKG (Plastic Pin Land Grid Array Package), or the like. The multi-layer substrate is often formed such that a substrate with a certain circuit pattern is insulatedly laminated to multiple layers and the laminated substrates are electrically connected between circuit patterns of each substrate by a through hole.
For example, a method for fabricating a laminated multi-layer substrate to fabricate a semiconductor package is disclosed in Japanese Patent Publication No. 10-223800 (U.S. Pat. No. 6,074,567). In this method, an inner circuit board having an opening is formed at a central portion and a bonding portion is formed adjacent to the opening to attach a gold wire connected to a semiconductor chip. After a cavity is formed by the opening by staking the inner circuit boards, an outer circuit board is laminated at an outermost layer to seal the cavity of the laminated inner circuit board.
Thereafter, a through bore is formed in the laminated body, which is fabricated as described above, an electroless-plated copper coating film and an electrolysis-plated copper coating film are formed at an inner side of the through bore, and a first plate nickel coating film is formed. At this time, since the bonding portion of the inner circuit board is covered with the outer circuit board, plating is not made thereon.
In this state, a circuit pattern forming process is performed by etching the laminated body, then coating a solder resist (S/R) thereon. Next, a certain portion of the outer circuit board corresponding to the opening of the inner circuit board is removed by a device, such as a router, to expose the cavity and the bonding portion. Finally, a plated nickel/gold coating film is formed at the bonding portion and at the through bore, thereby forming a through hole.
However, such a fabrication method makes it difficult to mechanically process. Additionally, previously formed circuit patterns are often damaged in this process due to impacts or other effects occurring during the process. Also, the plated nickel/gold coating layer is unnecessarily formed at the through hole.
In an effort to solve such problems, a second method has been tried. First, each substrate is laminated to form a cavity by upwardly opening the semiconductor package with an organic substance filled inside the cavity. Next, a through hole is formed, patterning is performed thereon, and the organic substance is removed. Finally, the lowermost substrate is processed, whereby the through hole is formed while bonding pads inside the cavity are protected.
However, also in this method, the lowermost substrate is subjected to processing and this method does not completely remove the organic substances filled in the cavity. Thus, since the organic substrates remaining in the cavity works as a foreign material when the nickel/gold coating layer is formed at the bonding portion, it deteriorates the quality of a semiconductor package.